| 2005 |
|---|
| 7 | EE | Masaharu Imai,
Akira Kitajima:
Verification Challenges in Configurable Processor Design with ASIP Meister.
CHARME 2005: 2 |
| 2002 |
|---|
| 6 | EE | Akira Kitajima,
Toshiyuki Sasaki,
Yoshinori Takeuchi,
Masaharu Imai:
Design of Application Specific CISC Using PEAS-III.
IEEE International Workshop on Rapid System Prototyping 2002: 12-17 |
| 2001 |
|---|
| 5 | EE | Akira Kitajima,
Makiko Itoh,
Jun Sato,
Akichika Shiomi,
Yoshinori Takeuchi,
Masaharu Imai:
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors.
ASP-DAC 2001: 649-654 |
| 4 | EE | Kozo Okano,
Yuko Kitahama,
Akira Kitajima,
Teruo Higashino,
Kenichi Taniguchi:
Formal Verification of CPU in Laboratory Work.
MSE 2001: 32-34 |
| 2000 |
|---|
| 3 | EE | Hisaaki Katagiri,
Keiichi Yasumoto,
Akira Kitajima,
Teruo Higashino,
Kenichi Taniguchi:
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization.
DAC 2000: 762-767 |
| 2 | EE | Makiko Itoh,
Shigeaki Higaki,
Yoshinori Takeuchi,
Akira Kitajima,
Masaharu Imai,
Jun Sato,
Akichika Shiomi:
PEAS-III: An ASIP Design Environment.
ICCD 2000: 430-436 |
| 1998 |
|---|
| 1 | | Keiichi Yasumoto,
Akira Kitajima,
Teruo Higashino,
Kenichi Taniguchi:
Hardware synthesis from protocol specifications in LOTOS.
FORTE 1998: 405-420 |
