| 2008 |
|---|
| 16 | EE | N. Sudha,
A. R. Mohan:
Design of a hardware accelerator for path planning on the Euclidean distance transform.
Journal of Systems Architecture - Embedded Systems Design 54(1-2): 253-264 (2008) |
| 2007 |
|---|
| 15 | | N. Sudha,
N. B. Puhan,
Hua Xia,
Xudong Jiang:
Local Partial Hausdorff Distance Measure Based on Binary Feature for Iris Recognition.
IICAI 2007: 621-629 |
| 14 | EE | E. P. Vivek,
N. Sudha:
Robust Hausdorff distance measure for face recognition.
Pattern Recognition 40(2): 431-442 (2007) |
| 2006 |
|---|
| 13 | EE | E. P. Vivek,
N. Sudha:
Gray Hausdorff distance measure for comparing face images.
IEEE Transactions on Information Forensics and Security 1(3): 342-349 (2006) |
| 2005 |
|---|
| 12 | EE | N. Sudha,
E. P. Vivek:
A High-Speed VLSI Array Architecture for Euclidean Metric-Based Hausdorff Distance Measures Between Images.
HiPC 2005: 180-189 |
| 11 | | E. P. Vivek,
N. Sudha:
Gray Hausdorff Distance Measures for Comparing Face Images.
IICAI 2005: 3103-3114 |
| 10 | EE | Chakka Siva Sai Prasanna,
N. Sudha,
V. Kamakoti:
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation.
VLSI Design 2005: 795-798 |
| 9 | EE | N. Sudha:
A pipelined array architecture for Euclidean distance transformation and its FPGA implementation.
Microprocessors and Microsystems 29(8-9): 405-410 (2005) |
| 2004 |
|---|
| 8 | EE | Chakka Siva Sai Prasanna,
N. Sudha,
V. Kamakoti:
A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN.
ICONIP 2004: 327-332 |
| 7 | EE | R. Suguna,
N. Sudha,
C. Chandra Sekhar:
A Fast and Efficient Face Detection Technique Using Support Vector Machine.
ICONIP 2004: 338-343 |
| 6 | EE | N. Sudha:
An ASIC Implementation of Kohonen's Map Based Color Image Compression.
VLSI Design 2004: 677-680 |
| 5 | EE | N. Sudha:
An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA Implementation.
VLSI Design 2004: 689-692 |
| 4 | EE | N. Sudha:
An ASIC implementation of Kohonen's map based colour image compression.
Real-Time Imaging 10(1): 31-39 (2004) |
| 2003 |
|---|
| 3 | EE | N. Sudha,
T. Srikanthan,
Babu Mailachalam:
A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation.
Journal of Systems Architecture 48(11-12): 337-352 (2003) |
| 2 | EE | N. Sudha:
Design of a Cellular Architecture for Fast Computation of the Skeleton.
VLSI Signal Processing 35(1): 61-73 (2003) |
| 1999 |
|---|
| 1 | | N. Sudha,
S. Nandi,
K. Sridharan:
A Parallel Algorithm to Construct Voronoi Diagram and Its VLSI Architecture.
ICRA 1999: 1683-1688 |
