2009 |
18 | EE | Andrew B. Kahng,
Chul-Hong Park,
Puneet Sharma,
Qinke Wang:
Lens aberration aware placement for timing yield.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
2007 |
17 | EE | Andrew B. Kahng,
Bao Liu,
Qinke Wang:
Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement.
IEEE Trans. VLSI Syst. 15(8): 904-912 (2007) |
2006 |
16 | EE | Charles J. Alpert,
Andrew B. Kahng,
Cliff C. N. Sze,
Qinke Wang:
Timing-driven Steiner trees are (practically) free.
DAC 2006: 389-392 |
15 | EE | Andrew B. Kahng,
Chul-Hong Park,
Puneet Sharma,
Qinke Wang:
Lens aberration aware timing-driven placement.
DATE 2006: 890-895 |
14 | EE | Andrew B. Kahng,
Qinke Wang:
A faster implementation of APlace.
ISPD 2006: 218-220 |
2005 |
13 | EE | Yongseok Cheon,
Pei-Hsin Ho,
Andrew B. Kahng,
Sherief Reda,
Qinke Wang:
Power-aware placement.
DAC 2005: 795-800 |
12 | | Andrew B. Kahng,
Sherief Reda,
Qinke Wang:
Architecture and details of a high quality, large-scale analytical placer.
ICCAD 2005: 891-898 |
11 | EE | Andrew B. Kahng,
Bao Liu,
Qinke Wang:
Supply Voltage Degradation Aware Analytical Placement.
ICCD 2005: 437-443 |
10 | EE | Andrew B. Kahng,
Sherief Reda,
Qinke Wang:
APlace: a general analytic placement framework.
ISPD 2005: 233-235 |
9 | EE | Hongyu Chen,
Chung-Kuan Cheng,
Andrew B. Kahng,
Ion I. Mandoiu,
Qinke Wang,
Bo Yao:
The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 588-599 (2005) |
8 | EE | Andrew B. Kahng,
Qinke Wang:
Implementation and extensibility of an analytic placer.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 734-747 (2005) |
2004 |
7 | EE | Hongyu Chen,
Chung-Kuan Cheng,
Andrew B. Kahng,
Makoto Mori,
Qinke Wang:
Optimal planning for mesh-based power distribution.
ASP-DAC 2004: 444-449 |
6 | EE | Andrew B. Kahng,
Qinke Wang:
An analytic placer for mixed-size placement and timing-driven placement.
ICCAD 2004: 565-572 |
5 | EE | Andrew B. Kahng,
Qinke Wang:
Implementation and extensibility of an analytic placer.
ISPD 2004: 18-25 |
4 | EE | Andrew B. Kahng,
Ion I. Mandoiu,
Qinke Wang,
Xu Xu,
Alexander Zelikovsky:
Multi-project reticle floorplanning and wafer dicing.
ISPD 2004: 70-77 |
2003 |
3 | EE | Hongyu Chen,
Chung-Kuan Cheng,
Andrew B. Kahng,
Ion I. Mandoiu,
Qinke Wang,
Bo Yao:
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology.
ICCAD 2003: 13-20 |
2 | EE | Hongyu Chen,
Chung-Kuan Cheng,
Andrew B. Kahng,
Ion I. Mandoiu,
Qinke Wang:
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.
SLIP 2003: 71-76 |
2000 |
1 | EE | Qinke Wang,
Lizhu Zhou:
Schema Based Data Storage and Query Optimization for Semi-structured Data.
Web-Age Information Management 2000: 389-398 |