| |
| 1991 | ||
|---|---|---|
| 1 | EE | Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima: Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. DAC 1991: 253-258 |
| 1 | Tatsuki Ishii | [1] |
| 2 | Yoshio Miki | [1] |
| 3 | Yasushi Ogawa | [1] |
| 4 | Yasuo Sato | [1] |
| 5 | Reiji Toyoshima | [1] |