| |
| 2005 | ||
|---|---|---|
| 2 | EE | Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. Integration 38(3): 439-449 (2005) |
| 2004 | ||
| 1 | EE | Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. ACM Great Lakes Symposium on VLSI 2004: 220-223 |
| 1 | Yoji Kajitani | [1] [2] |
| 2 | Yukiko Kubo | [1] [2] |
| 3 | Hiroshi Miyashita | [1] [2] |