Hafijur Rahman

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2004

1 Hafijur Rahman, Chaitali Chakrabarti: A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. ISCAS (2) 2004: 297-300

2004
1		Hafijur Rahman, Chaitali Chakrabarti: A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. ISCAS (2) 2004: 297-300

Coauthor Index

1 Chaitali Chakrabarti [1]