Manuel E. Acacio

2008
38		Alberto Ros, Manuel E. Acacio, José M. García: Scalable Directory Organization for Tiled CMP Architectures. CDES 2008: 112-118
37		Juan Fernández, Manuel E. Acacio, Gregorio Bernabé, José L. Abellán, Joaquin Franco: Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla. CSC 2008: 167-173
36	EE	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: A fault-tolerant directory-based cache coherence protocol for CMP architectures. DSN 2008: 267-276
35	EE	J. Rubén Titos Gil, Manuel E. Acacio, José M. García: Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC 2008: 541-554
34	EE	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. HiPC 2008: 555-568
33	EE	José L. Abellán, Juan Fernández, Manuel E. Acacio: Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. ICCS (1) 2008: 456-465
32	EE	Antonio Flores, Manuel E. Acacio, Juan L. Aragón: Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP 2008: 295-303
31	EE	Alberto Ros, Manuel E. Acacio, José M. García: DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS 2008: 1-11
30	EE	José L. Abellán, Juan Fernández, Manuel E. Acacio: CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. PDP 2008: 261-268
29	EE	J. Rubén Titos Gil, Manuel E. Acacio, José M. García Carrasco: Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP 2008: 30-37
28	EE	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. IEEE Trans. Parallel Distrib. Syst. 19(8): 1044-1056 (2008)
27	EE	Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García: Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distrib. Comput. 68(11): 1413-1424 (2008)
26	EE	Antonio Flores, Juan L. Aragón, Manuel E. Acacio: An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. The Journal of Supercomputing 45(3): 341-364 (2008)
2007
25	EE	Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) 2007: 752-757
24	EE	Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. HPCA 2007: 157-168
23	EE	Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC 2007: 133-146
22	EE	Alberto Ros, Manuel E. Acacio, José M. García: Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC 2007: 147-160
21	EE	Gregorio Bernabé, Ricardo Fernández, José M. García, Manuel E. Acacio, José González: An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Computing 33(1): 54-72 (2007)
2006
20	EE	Alberto Ros, Manuel E. Acacio, José M. García: An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers 2006: 321-330
19	EE	Francisco J. Villa, Manuel E. Acacio, José M. García: On the Evaluation of Dense Chip-Multiprocessor Architectures. ICSAMOS 2006: 21-27
2005
18	EE	Alberto Ros, Manuel E. Acacio, José M. García: A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. Euro-Par 2005: 582-591
17	EE	Francisco J. Villa, Manuel E. Acacio, José M. García: Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. HPCC 2005: 213-222
16	EE	Ricardo Fernández, José M. García, Gregorio Bernabé, Manuel E. Acacio: Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. PDP 2005: 76-83
15	EE	Manuel E. Acacio, José González, José M. García, José Duato: A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 16(1): 67-79 (2005)
14	EE	Francisco J. Villa, Manuel E. Acacio, José M. García: Evaluating IA-32 web servers through simics: a practical experience. Journal of Systems Architecture 51(4): 251-264 (2005)
2004
13	EE	Francisco J. Villa, Manuel E. Acacio, José M. García: On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs. International Conference on Computational Science 2004: 541-544
12	EE	Manuel E. Acacio, José González, José M. García, José Duato: An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. IEEE Trans. Parallel Distrib. Syst. 15(8): 755-768 (2004)
2002
11	EE	Manuel E. Acacio, José González, José M. García, José Duato: The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. IEEE PACT 2002: 155-164
10	EE	Manuel E. Acacio, José González, José M. García, José Duato: A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. IPDPS 2002
9	EE	Manuel E. Acacio, José González, José M. García, José Duato: Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. PDP 2002: 368-375
8	EE	Manuel E. Acacio, José González, José M. García, José Duato: Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. SC 2002: 1-12
7	EE	Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel: MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing. Future Generation Comp. Syst. 18(3): 317-333 (2002)
2001
6	EE	Manuel E. Acacio, José González, José M. García, José Duato: A New Scalable Directory Architecture for Large-Scale Multiprocessors. HPCA 2001: 97-106
1999
5	EE	Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel: An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet. ACPC 1999: 570-571
4	EE	Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio, Óscar Cánovas Reverte: P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations. IPPS/SPDP 1999: 563-568
3		Manuel E. Acacio, Pedro E. López-de-Teruel, José M. García, Óscar Cánovas Reverte: The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations. PDPTA 1999: 1730-1736
2		Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio: The Parallel EM Algorithm and its Applications in Computer Vision. PDPTA 1999: 571-578
1		Manuel E. Acacio, José M. García, Pedro E. López-de-Teruel: A Performance Evaluation of P-EDR in Different Parallel Environments. PDPTA 1999: 744-750

Coauthor Index

1	José L. Abellán	[30] [33] [37]
2	Juan L. Aragón	[23] [25] [26] [32]
3	Gregorio Bernabé	[16] [21] [37]
4	José M. García Carrasco	[29]
5	José Duato	[6] [8] [9] [10] [11] [12] [15] [24] [28] [34] [36]
6	Ricardo Fernández	[16] [21]
7	Antonio Flores	[23] [25] [26] [32]
8	Joaquin Franco	[37]
9	José M. García	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [24] [27] [28] [31] [34] [35] [36] [38]
10	J. Rubén Titos Gil	[29] [35]
11	José González	[6] [8] [9] [10] [11] [12] [15] [21]
12	Pedro E. López-de-Teruel	[1] [2] [3] [4] [5] [7]
13	Ricardo Fernández Pascual	[24] [27] [28] [34] [36]
14	Juan Fernández Peinador (Juan Fernández)	[30] [33] [37]
15	Óscar Cánovas Reverte (Oscar Cánovas Reverte)	[3] [4] [5] [7]
16	Alberto Ros	[18] [20] [22] [27] [31] [38]
17	Francisco J. Villa	[13] [14] [17] [19]