2007 |
18 | EE | Doron Drusinsky,
Man-tak Shing:
Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test Generation.
IEEE International Workshop on Rapid System Prototyping 2007: 82-88 |
17 | EE | Thomas W. Otani,
Mikhail Auguston,
Thomas S. Cook,
Doron Drusinsky,
James Bret Michael,
M. Shing:
A design pattern for using non-developmental items in real-time Java.
JTRES 2007: 135-143 |
2006 |
16 | EE | Doron Drusinsky,
Man-tak Shing,
Kadir Alpaslan Demir:
Creation and Validation of Embedded Assertion Statecharts.
IEEE International Workshop on Rapid System Prototyping 2006: 17-23 |
15 | EE | Doron Drusinsky:
On-line Monitoring of Metric Temporal Logic with Time-Series Constraints Using Alternating Finite Automata.
J. UCS 12(5): 482-498 (2006) |
2005 |
14 | EE | Doron Drusinsky,
Man-tak Shing,
Kadir Alpaslan Demir:
Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP.
IEEE International Workshop on Rapid System Prototyping 2005: 105-110 |
13 | EE | Doron Drusinsky:
Semantics and Runtime Monitoring of TLCharts: Statechart Automata with Temporal Logic Conditioned Transitions.
Electr. Notes Theor. Comput. Sci. 113: 3-21 (2005) |
2004 |
12 | EE | Doron Drusinsky,
Man-tak Shing:
TLCharts: Armor-plating Harel Statecharts with Temporal Logic Conditions.
IEEE International Workshop on Rapid System Prototyping 2004: 29-36 |
11 | EE | Doron Drusinsky:
Automatic Simulation of Network Problems in UDP-Based Java Programs Temporal Logic and Natural Language Conditioned Transitions.
IPDPS 2004 |
10 | EE | Guillaume P. Brat,
Doron Drusinsky,
Dimitra Giannakopoulou,
Allen Goldberg,
Klaus Havelund,
Michael R. Lowry,
Corina S. Pasareanu,
Arnaud Venet,
Willem Visser,
Richard Washington:
Experimental Evaluation of Verification and Validation Tools on Martian Rover Software.
Formal Methods in System Design 25(2-3): 167-198 (2004) |
2003 |
9 | EE | Cyrille Artho,
Doron Drusinsky,
Allen Goldberg,
Klaus Havelund,
Michael R. Lowry,
Corina S. Pasareanu,
Grigore Rosu,
Willem Visser:
Experiments with Test Case Generation and Runtime Analysis.
Abstract State Machines 2003: 87-107 |
8 | EE | Doron Drusinsky:
Monitoring Temporal Rules Combined with Time Series.
CAV 2003: 114-117 |
7 | EE | Doron Drusinsky,
Man-tak Shing:
Verification of Timing Properties in Rapid System Prototyping.
IEEE International Workshop on Rapid System Prototyping 2003: 47- |
6 | EE | Doron Drusinsky,
Garth Watney:
Applying Run-Time Monitoring to the Deep-Impact Fault Protection Engine.
SEW 2003: 127 |
5 | EE | Doron Drusinsky,
Man-tak Shing:
Monitoring Temporal Logic Specifications Combined with Time Series Constraints.
J. UCS 9(11): 1261-1276 (2003) |
2000 |
4 | | Doron Drusinsky:
The Temporal Rover and the ATG Rover.
SPIN 2000: 323-330 |
1994 |
3 | EE | Doron Drusinsky,
David Harel:
On the Power of Bounded Concurrency I: Finite Automata.
J. ACM 41(3): 517-539 (1994) |
1989 |
2 | EE | Doron Drusinsky,
David Harel:
Using statecharts for hardware description and synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 798-807 (1989) |
1988 |
1 | | Doron Drusinsky,
David Harel:
On the Power of Cooperative Concurrency.
Concurrency 1988: 74-103 |