2008 |
28 | EE | Xiaotong Zhuang,
Suhyun Kim,
Mauricio J. Serrano,
Jong-Deok Choi:
Perfdiff: a framework for performance difference analysis in a virtual machine environment.
CGO 2008: 4-13 |
2007 |
27 | EE | Xiaotong Zhuang,
Santosh Pande:
Power-efficient prefetching for embedded processors.
ACM Trans. Embedded Comput. Syst. 6(1): (2007) |
26 | EE | Xiaotong Zhuang,
Santosh Pande:
Allocating architected registers through differential encoding.
ACM Trans. Program. Lang. Syst. 29(2): (2007) |
25 | EE | Xiaotong Zhuang,
Hsien-Hsin S. Lee:
Reducing Cache Pollution via Dynamic Data Prefetch Filtering.
IEEE Trans. Computers 56(1): 18-31 (2007) |
2006 |
24 | EE | Tao Zhang,
Xiaotong Zhuang,
Santosh Pande:
Compiler Optimizations to Reduce Security Overhead.
CGO 2006: 346-357 |
23 | EE | Xiaotong Zhuang,
Santosh Pande:
A Scalable Priority Queue Architecture for High Speed Network Processing.
INFOCOM 2006 |
22 | EE | R. Collins,
F. Alegre,
Xiaotong Zhuang,
Santosh Pande:
Compiler assisted dynamic management of registers for network processors.
IPDPS 2006 |
21 | EE | Xiaotong Zhuang,
Santosh Pande:
Effective thread management on network processors with compiler analysis.
LCTES 2006: 72-82 |
20 | EE | Xiaotong Zhuang,
Tao Zhang,
Santosh Pande:
Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection.
MICRO 2006: 113-122 |
19 | EE | Xiaotong Zhuang,
Mauricio J. Serrano,
Harold W. Cain,
Jong-Deok Choi:
Accurate, efficient, and adaptive calling context profiling.
PLDI 2006: 263-271 |
18 | EE | Xiaotong Zhuang,
Santosh Pande:
Parallelizing load/stores on dual-bank memory embedded processors.
ACM Trans. Embedded Comput. Syst. 5(3): 613-657 (2006) |
2005 |
17 | EE | Tao Zhang,
Xiaotong Zhuang,
Santosh Pande,
Wenke Lee:
Anomalous path detection with hardware support.
CASES 2005: 43-54 |
16 | EE | Tao Zhang,
Xiaotong Zhuang,
Santosh Pande:
Building Intrusion-Tolerant Secure Software.
CGO 2005: 255-266 |
15 | EE | Xiaotong Zhuang,
Santosh Pande:
Differential register allocation.
PLDI 2005: 168-179 |
14 | EE | Xiaotong Zhuang,
Vincenzo Liberatore:
A Recursion-Based Broadcast Paradigm in Wormhole Routed Networks.
IEEE Trans. Parallel Distrib. Syst. 16(11): 1034-1052 (2005) |
2004 |
13 | EE | Xiaotong Zhuang,
Tao Zhang,
Santosh Pande:
HIDE: an infrastructure for efficiently protecting information leakage on the address bus.
ASPLOS 2004: 72-84 |
12 | EE | Xiaotong Zhuang,
Tao Zhang,
Hsien-Hsin S. Lee,
Santosh Pande:
Hardware assisted control flow obfuscation for embedded processors.
CASES 2004: 292-302 |
11 | EE | Xiaotong Zhuang,
Tao Zhang,
Santosh Pande:
Hardware-managed register allocation for embedded processors.
LCTES 2004: 192-201 |
10 | EE | Xiaotong Zhuang,
Santosh Pande:
Power-efficient prefetching via bit-differential offset assignment on embedded processors.
LCTES 2004: 67-77 |
9 | EE | Xiaotong Zhuang,
Santosh Pande:
Balancing register allocation across threads for a multithreaded network processor.
PLDI 2004: 289-300 |
2003 |
8 | EE | Xiaotong Zhuang,
Santosh Pande:
Compiler Scheduling of Mobile Agents for Minimizing Overheads.
ICDCS 2003: 600- |
7 | EE | Xiaotong Zhuang,
Hsien-Hsin S. Lee:
A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches.
ICPP 2003: 286-293 |
6 | EE | Xiaotong Zhuang,
Santosh Pande:
Resolving Register Bank Conflicts for a Network Processor.
IEEE PACT 2003: 269- |
5 | EE | Xiaotong Zhuang,
ChokSheak Lau,
Santosh Pande:
Storage assignment optimizations through variable coalescence for embedded processors.
LCTES 2003: 220-231 |
2002 |
4 | EE | Xiaotong Zhuang,
Jian Liu:
WRAPS Scheduling and Its Efficient Implementation on Network Processors.
HiPC 2002: 252-263 |
3 | EE | Xiaotong Zhuang,
Santosh Pande,
John S. Greenland Jr.:
A Framework for Parallelizing Load/Stores on Embedded Processors.
IEEE PACT 2002: 68- |
2 | EE | Xiaotong Zhuang,
Vincenzo Liberatore:
A Recursion-Based Broadcast Paradigm in Wormhole Routed Mesh/Torus Networks.
IPDPS 2002 |
1 | EE | Weidong Shi,
Xiaotong Zhuang,
Indrani Paul,
Karsten Schwan:
Efficient Implementation of Packet Scheduling Algorithm on High-Speed Programmable Network Processors.
MMNS 2002: 184-197 |