| 2008 |
|---|
| 3 | EE | Jiayi Liu,
Sheqin Dong,
Xianlong Hong,
Yibo Wang,
Ou He,
Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology.
ASP-DAC 2008: 772-775 |
| 2 | EE | Ou He,
Sheqin Dong,
Jinian Bian,
Satoshi Goto,
Chung-Kuan Cheng:
A novel fixed-outline floorplanner with zero deadspace for hierarchical design.
ICCAD 2008: 16-23 |
| 2007 |
|---|
| 1 | EE | Ou He,
Sheqin Dong,
Jinian Bian,
Yuchun Ma,
Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement.
ACM Great Lakes Symposium on VLSI 2007: 564-569 |
