2002 | ||
---|---|---|
2 | EE | Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton: Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI 2002: 1-6 |
1995 | ||
1 | John H. Edmondson, Paul I. Rubinfeld, Peter J. Bannon, Bradley J. Benschneider, Debra Bernstein, Ruben W. Castelino, Elizabeth M. Cooper, Daniel E. Dever, Dale R. Donchin, Timothy C. Fischer, Anil K. Jain, Shekhar Mehta, Jeanne E. Meyer, Ronald P. Preston, Vidya Rajagopalan, Chandrasekhara Somanathan, Scott A. Taylor, Gilbert M. Wolrich: Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor Digital Technical Journal 7(1): 0- (1995) |
1 | Dan Bailey | [2] |
2 | Peter J. Bannon | [1] |
3 | Bradley J. Benschneider | [1] |
4 | Debra Bernstein | [1] |
5 | David Bertucci | [2] |
6 | Gabriel P. Bischoff | [2] |
7 | Ruben W. Castelino | [1] |
8 | Elizabeth M. Cooper | [1] |
9 | Dale R. Donchin | [1] |
10 | John H. Edmondson | [1] |
11 | Timothy C. Fischer | [1] |
12 | Mike Gowan | [2] |
13 | Joel Grodstein | [2] |
14 | Anil K. Jain | [1] |
15 | Roy Lane | [2] |
16 | Brian Lilly | [2] |
17 | Sue Lowell | [2] |
18 | Shekhar Mehta | [1] |
19 | Jeanne E. Meyer | [1] |
20 | Shannon V. Morton | [2] |
21 | Krishna Nagalla | [2] |
22 | Ronald P. Preston | [1] |
23 | Vidya Rajagopalan | [1] |
24 | Rachid Rayess | [2] |
25 | Paul I. Rubinfeld | [1] |
26 | Rahul Shah | [2] |
27 | Linda Shattuck | [2] |
28 | Emily Shriver | [2] |
29 | Chandrasekhara Somanathan | [1] |
30 | Scott A. Taylor | [1] |
31 | Tad Truex | [2] |
32 | Gilbert M. Wolrich | [1] |
33 | Shi-Huang Yin | [2] |