| 2007 |
|---|
| 6 | EE | L. E. M. Brackenbury,
W. Shao:
Lowering power in an experimental RISC processor.
Microprocessors and Microsystems 31(5): 360-368 (2007) |
| 2004 |
|---|
| 5 | EE | Aristides Efthymiou,
W. Suntiamorntut,
Jim D. Garside,
L. E. M. Brackenbury:
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.
ASYNC 2004: 207-215 |
| 2001 |
|---|
| 4 | EE | P. A. Riocreux,
L. E. M. Brackenbury,
J. Mike Cumpstey,
Stephen B. Furber:
A Low-Power Self-Timed Viterbi Decoder.
ASYNC 2001: 15-24 |
| 3 | EE | Mike J. G. Lewis,
L. E. M. Brackenbury:
Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank.
ASYNC 2001: 4-14 |
| 2000 |
|---|
| 2 | EE | Mike J. G. Lewis,
L. E. M. Brackenbury:
An Instruction Buffer for a Low-Power DSP.
ASYNC 2000: 176- |
| 1999 |
|---|
| 1 | EE | Mike J. G. Lewis,
Jim D. Garside,
L. E. M. Brackenbury:
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.
ASYNC 1999: 27-35 |
