| |
| 2008 | ||
|---|---|---|
| 2 | EE | Mayur Bubna, Sudip Roy, Naresh Shenoy, Subhra Mazumdar: A layout-aware physical design method for constructing feasible QCA circuits. ACM Great Lakes Symposium on VLSI 2008: 243-248 |
| 1 | EE | Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay: An efficient greedy approach to PLA folding. ISCAS 2008: 1356-1359 |
| 1 | Santanu Chattopadhyay | [1] |
| 2 | Subhra Mazumdar | [2] |
| 3 | Sudip Roy | [2] |
| 4 | Naresh Shenoy | [1] [2] |