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Naresh Shenoy

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2008
2EEMayur Bubna, Sudip Roy, Naresh Shenoy, Subhra Mazumdar: A layout-aware physical design method for constructing feasible QCA circuits. ACM Great Lakes Symposium on VLSI 2008: 243-248
1EEMayur Bubna, Naresh Shenoy, Santanu Chattopadhyay: An efficient greedy approach to PLA folding. ISCAS 2008: 1356-1359

Coauthor Index

1Mayur Bubna [1] [2]
2Santanu Chattopadhyay [1]
3Subhra Mazumdar [2]
4Sudip Roy [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)