| 2009 |
|---|
| 3 | EE | Di Wang,
Vyas Venkataraman,
Zhen Wang,
Wei Qin,
Hangsheng Wang,
Mrinal Bose,
Jayanta Bhadra:
Accelerating multi-party scheduling for transaction-level modeling.
ACM Great Lakes Symposium on VLSI 2009: 339-344 |
| 2008 |
|---|
| 2 | EE | Konrad J. Kulikowski,
Vyas Venkataraman,
Zhen Wang,
Alexander Taubin:
Power Balanced Gates Insensitive to Routing Capacitance Mismatch.
DATE 2008: 1280-1285 |
| 1 | EE | Konrad J. Kulikowski,
Vyas Venkataraman,
Zhen Wang,
Alexander Taubin,
Mark G. Karpovsky:
Asynchronous balanced gates tolerant to interconnect variability.
ISCAS 2008: 3190-3193 |
