| |
| 2006 | ||
|---|---|---|
| 2 | EE | Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang: Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS 2006 |
| 2004 | ||
| 1 | EE | Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang: 64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC 2004: 65-68 |
| 1 | Kuo-Hsing Cheng | [1] [2] |
| 2 | Shun-Wen Cheng | [1] |
| 3 | Shu-Yu Jiang | [2] |