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| 2007 | ||
|---|---|---|
| 3 | EE | Yong Dou, Jinhui Xu, Guiming Wu: The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. ARC 2007: 155-166 |
| 2 | EE | Miao Wang, Guiming Wu, Zhiying Wang: Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors. ISPA 2007: 946-957 |
| 2006 | ||
| 1 | EE | Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong: Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. Asia-Pacific Computer Systems Architecture Conference 2006: 567-573 |
| 1 | Yazhuo Dong | [1] |
| 2 | Yong Dou | [1] [3] |
| 3 | Miao Wang | [2] |
| 4 | Zhiying Wang | [2] |
| 5 | Jinhui Xu | [1] [3] |