Gi-Yong Song

2007
6	EE	Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song: Design of a Reversible PLD Architecture. ARC 2007: 85-90
2006
5	EE	Jae-Jin Lee, Gi-Yong Song: High-Level Synthesis Using SPARK and Systolic Array. ARC 2006: 455-460
4	EE	Jae-Jin Lee, Gi-Yong Song: Super Semi-systolic Array-Based Application-Specific PLD Architecture. ARC 2006: 461-466
2005
3	EE	Jae-Jin Lee, Gi-Yong Song: Design of an application-specific PLD architecture. ASP-DAC 2005: 1244-1247
2	EE	Jae-Jin Lee, Gi-Yong Song: A New Application-Specific PLD Architecture. IEICE Transactions 88-A(6): 1425-1433 (2005)
2004
1	EE	Jae-Jin Lee, Gi-Yong Song: Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. FPGA 2004: 249

Coauthor Index

1	Dong-Guk Hwang	[6]
2	Jae-Jin Lee	[1] [2] [3] [4] [5] [6]