Ing-Chao Lin

2006
2	EE	Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780
2005
1	EE	Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan: A power estimation methodology for systemC transaction level models. CODES+ISSS 2005: 142-147

Coauthor Index

1	Nagu R. Dhanwada	[1] [2]
2	Vijay Narayanan	[1]
3	Suresh Srinivasan	[2]
4	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[2]