| 2000 |
|---|
| 7 | EE | Luiz André Barroso,
Kourosh Gharachorloo,
Robert McNamara,
Andreas Nowatzyk,
Shaz Qadeer,
Barton Sano,
Scott Smith,
Robert Stets,
Ben Verghese:
Piranha: a scalable architecture based on single-chip multiprocessing.
ISCA 2000: 282-293 |
| 6 | EE | Chia-Lin Yang,
Barton Sano,
Alvin R. Lebeck:
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.
IEEE Trans. Computers 49(9): 934-946 (2000) |
| 1998 |
|---|
| 5 | EE | Chia-Lin Yang,
Barton Sano,
Alvin R. Lebeck:
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.
MICRO 1998: 14-24 |
| 1996 |
|---|
| 4 | | Bruce K. Holmer,
Barton Sano,
Michael J. Carlton,
Peter Van Roy,
Alvin M. Despain:
Design and Analysis of Hardware for High-Performance Prolog.
J. Log. Program. 29(1-3): 107-139 (1996) |
| 1995 |
|---|
| 3 | | Apoorv Srivastava,
Yong-Seon Koh,
Barton Sano,
Alvin M. Despain:
190-MHz CMOS 4-Kbyte Pipelined Caches.
ISCAS 1995: 1053-1056 |
| 1993 |
|---|
| 2 | EE | Barton Sano,
Alvin M. Despain:
The 16-fold way: a microparallel taxonomy.
MICRO 1993: 60-69 |
| 1990 |
|---|
| 1 | | Bruce K. Holmer,
Barton Sano,
Michael J. Carlton,
Peter Van Roy,
Ralph Clarke Haygood,
William R. Bush,
Alvin M. Despain,
Joan M. Pendleton,
Tep P. Dobry:
Fast Prolog with an Extended General Purpose Architecture.
ISCA 1990: 282-291 |
