Formal Methods in System Design, Volume 7

Volume 7, Number 1/2, August 1995

• David M. Russinoff: A Formalization of a Subset of VHDL in the Boyer-Moore Logic. 7-25 BibTeX
• Peter T. Breuer, Luis Sánchez Fernández, Carlos Delgado Kloos: A Simple Denotational Semantics, Proof Theory and a Validation Condition Generator for Unit-Delay VHDL. 27-51 BibTeX
• Dominique Borrione, Ashraf M. Salem: Denotational Semantics of a Synchronous VHDL Subset. 53-71 BibTeX
• Ralf Reetz, Thomas Kropf: A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL. 73-99 BibTeX
• Serafín Olcoz, José Manuel Colom: A Colored Petri Net Model of VHDL. 101-123 BibTeX
• Gert Döhmen, Ronald Herrmann, Hergen Pargmann: Translating VHDL into Functional Symbolic Finite-State Models. 125-148 BibTeX

Volume 7, Number 3, November 1995

• Scott F. Smith, Amy E. Zwarico: Correct Compilation of Specifications to Deterministic Asynchronous Circuits. 155-226 BibTeX
• Patrice Godefroid, Gerard J. Holzmann, Didier Pirottin: State-Space Caching Revisited. 227-241 BibTeX
• Huimin Lin: PAM: A Process Algebra Manipulator. 243-259 BibTeX