2009 | ||
---|---|---|
3 | EE | Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau: Measuring and modeling variabilityusing low-cost FPGAs. FPGA 2009: 286 |
2007 | ||
2 | EE | Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau: Estimating design time for system circuits. VLSI-SoC 2007: 60-65 |
2005 | ||
1 | EE | Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau: uComplexity: Estimating Processor Design Effort. MICRO 2005: 209-218 |
1 | Michael Brown | [3] |
2 | Brian Greskamp | [2] |
3 | Matthew R. Guthaus | [3] |
4 | Francisco J. Mesa-Martinez | [1] [2] |
5 | Jose Renau | [1] [2] [3] |
6 | Josep Torrellas | [2] |