| |
| 2007 | ||
|---|---|---|
| 3 | EE | Ales Smrcka, Tomás Vojnar: Verifying Parametrised Hardware Designs Via Counter Automata. Haifa Verification Conference 2007: 51-68 |
| 2006 | ||
| 2 | EE | Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák: Verifying VHDL Designs with Multiple Clocks in SMV. FMICS/PDMC 2006: 148-164 |
| 2005 | ||
| 1 | EE | Petr Matousek, Ales Smrcka, Tomás Vojnar: High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design. CHARME 2005: 371-375 |
| 1 | Petr Matousek | [1] [2] |
| 2 | Vojtech Rehák | [2] |
| 3 | Z. Rehák | [2] |
| 4 | David Safránek | [2] |
| 5 | Tomás Vojnar | [1] [2] [3] |