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Chia-Tsun Wu

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2006
3EEChia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. ISCAS 2006
2EEWei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu: A portable all-digital pulsewidth control loop for SOC applications. ISCAS 2006
2005
1EEChia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A scalable DCO design for portable ADPLL designs. ISCAS (6) 2005: 5449-5452

Coauthor Index

1Wei Wang [1] [2] [3]
2I-Chyn Wey [1] [2] [3]
3An-Yeu Wu [1] [2] [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)