| |
| 2008 | ||
|---|---|---|
| 7 | EE | Thomas Poonnen, Adly T. Fam: An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach. Journal of Systems Architecture - Embedded Systems Design 54(12): 1122-1128 (2008) |
| 6 | EE | Adly T. Fam, Indranil Sarkar: A new class of interlaced complementary codes based on components with unity peak sidelobes. Signal Processing 88(2): 307-314 (2008) |
| 2007 | ||
| 5 | EE | Thomas Poonnen, Adly T. Fam: A Novel VLSI Divide and Conquer Implementation of the Iterative Array Multiplier. ITNG 2007: 723-728 |
| 2006 | ||
| 4 | EE | Indranil Sarkar, Adly T. Fam: The interlaced chirp Z transform. Signal Processing 86(9): 2221-2232 (2006) |
| 2005 | ||
| 3 | EE | Peyman Arian, Tapio Saramäki, Adly T. Fam: A decomposition technique for cascaded IIR-like filter blocks generating linear-phase FIR filters. ISCAS (3) 2005: 2008-2011 |
| 1990 | ||
| 2 | Tein-Hsiang Lin, Adly T. Fam: A Hierarchical Approach for the Design of Two-Dimensional Fault-Tolerant Systolic Arrays. ICPP (1) 1990: 565-566 | |
| 1987 | ||
| 1 | Adly T. Fam: Optimal Partitioning and Redundancy Removal in Computing Partial Sums. IEEE Trans. Computers 36(10): 1137-1143 (1987) | |
| 1 | Peyman Arian | [3] |
| 2 | Tein-Hsiang Lin | [2] |
| 3 | Thomas Poonnen | [5] [7] |
| 4 | Tapio Saramäki | [3] |
| 5 | Indranil Sarkar | [4] [6] |