| |
| 2008 | ||
|---|---|---|
| 1 | EE | Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao: Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED 2008: 307-308 |
| 1 | Sukumar Jairam | [1] |
| 2 | Jagdish C. Rao | [1] |
| 3 | Madhusudan Rao | [1] |
| 4 | Jithendra Srinivas | [1] |
| 5 | H. Udayakumar | [1] |