2009 | ||
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2 | EE | Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao: Clock gating effectiveness metrics: Applications to power optimization. ISQED 2009: 482-487 |
2008 | ||
1 | EE | Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao: Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED 2008: 307-308 |
1 | Sukumar Jairam | [1] [2] |
2 | Jagdish C. Rao | [1] [2] |
3 | Madhusudan Rao | [1] [2] |
4 | H. Udayakumar | [1] [2] |
5 | Parimala Vishwanath | [1] |