| 2008 |
|---|
| 18 | EE | Meng-Chun Lin,
Lan-Rong Dung:
On VLSI design of rank-order filtering using DCRAM architecture.
Integration 41(2): 193-209 (2008) |
| 17 | EE | Tsung-Hsi Chiang,
Lan-Rong Dung:
Verification of Dataflow Scheduling.
International Journal of Software Engineering and Knowledge Engineering 18(6): 737-758 (2008) |
| 2007 |
|---|
| 16 | EE | Tsung-Hsi Chiang,
Lan-Rong Dung:
Verification method of dataflow algorithms in high-level synthesis.
Journal of Systems and Software 80(8): 1256-1270 (2007) |
| 2006 |
|---|
| 15 | EE | Meng-Chun Lin,
Lan-Rong Dung,
Hsuan-Po Lin:
A Subsample-based Motion Estimation for Quality-Stationary Video Coding.
APCCAS 2006: 1256-1259 |
| 14 | EE | Tsung-Hsi Chiang,
Lan-Rong Dung:
System-level verification on high-level synthesis of dataflow graph.
ISCAS 2006 |
| 13 | EE | Lan-Rong Dung,
Hsueh-Chih Yang:
A Parallel-In Folding Technique for High-Order FIR Filter Implementation.
IEICE Transactions 89-A(12): 3659-3665 (2006) |
| 12 | EE | Hsien-Wen Cheng,
Lan-Rong Dung:
A Power-Aware Motion Estimation Architecture Using Content-based Subsampling.
J. Inf. Sci. Eng. 22(4): 799-818 (2006) |
| 2005 |
|---|
| 11 | EE | Hsueh-Chih Yang,
Lan-Rong Dung:
On multiple-voltage high-level synthesis using algorithmic transformations.
ASP-DAC 2005: 872-876 |
| 10 | EE | Jieh-Hwang Yen,
Lan-Rong Dung,
Chi-Yuan Shen:
Design of power-aware multiplier with graceful quality-power trade-offs.
ISCAS (2) 2005: 1642-1645 |
| 9 | EE | Teng-Hung Chang,
Lan-Rong Dung,
Jwin-Yen Guo:
On reducing leakage quantization noise of multistage Sigma-Delta modulator using nonlinear oscillation.
ISCAS (3) 2005: 2555-2558 |
| 8 | EE | Tsung-Hsi Chiang,
Lan-Rong Dung,
Ming-Feng Yaung:
Modeling and formal verification of dataflow graph in system-level design using Petri net.
ISCAS (6) 2005: 5674-5677 |
| 7 | EE | Teng-Hung Chang,
Lan-Rong Dung:
Dynamic Range Improvement of Multistage Multibit Modulator for Low Oversampling Ratios.
IEICE Transactions 88-A(2): 451-460 (2005) |
| 2004 |
|---|
| 6 | EE | Hsien-Wen Cheng,
Lan-Rong Dung:
A power-aware ME architecture using subsample algorithm.
ISCAS (3) 2004: 821-824 |
| 2002 |
|---|
| 5 | EE | Hsien-Wen Cheng,
Lan-Rong Dung:
EFBLA: A Two-Phase Matching Algorithm for Fast Motion Estimation.
IEEE Pacific Rim Conference on Multimedia 2002: 112-119 |
| 4 | EE | Shiuh-Rong Huang,
Lan-Rong Dung:
VLSI Implementation for MAC-Level DWT Architecture.
ISVLSI 2002: 101-106 |
| 1996 |
|---|
| 3 | EE | Lan-Rong Dung,
Vijay K. Madisetti:
Conceptual Prototyping of Scalable Embedded DSP Systems.
IEEE Design & Test of Computers 13(3): 54-65 (1996) |
| 2 | EE | Thomas Egolf,
M. Pettigrew,
James Debardelaben,
R. Hezar,
S. Famorzadeh,
A. Kavipurapu,
Moinul H. Khan,
Lan-Rong Dung,
K. Balemarthy,
N. Desai,
Vijay K. Madisetti:
VHDL-based rapid system prototyping.
VLSI Signal Processing 14(2): 125-156 (1996) |
| 1994 |
|---|
| 1 | | Wen-Zen Shen,
Yi-Hsin Tao,
Lan-Rong Dung:
On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design.
ISCAS 1994: 171-174 |
