| 2002 |
|---|
| 26 | EE | Mark Oskin,
Frederic T. Chong,
Matthew K. Farrens:
Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation.
J. Instruction-Level Parallelism 4: (2002) |
| 2001 |
|---|
| 25 | EE | Hsien-Hsin S. Lee,
Gary S. Tyson,
Matthew K. Farrens:
Improving Bandwidth Utilization using Eager Writeback.
J. Instruction-Level Parallelism 3: (2001) |
| 2000 |
|---|
| 24 | EE | Kevin D. Rich,
Matthew K. Farrens:
Code Partitioning in Decoupled Compilers.
Euro-Par 2000: 1008-1017 |
| 23 | EE | Kevin D. Rich,
Matthew K. Farrens:
The Decoupled-Style Prefetch Architecture (Research Note).
Euro-Par 2000: 989-993 |
| 22 | EE | Michael Haungs,
Phil Sallee,
Matthew K. Farrens:
Branch Transition Rate: A New Metric for Improved Branch Classification Analysis.
HPCA 2000: 241-250 |
| 21 | EE | Mark Oskin,
Frederic T. Chong,
Matthew K. Farrens:
HLS: combining statistical and symbolic simulation to guide microprocessor designs.
ISCA 2000: 71-82 |
| 20 | EE | Hsien-Hsin S. Lee,
Gary S. Tyson,
Matthew K. Farrens:
Eager writeback - a technique for improving bandwidth utilization.
MICRO 2000: 11-21 |
| 1999 |
|---|
| 19 | EE | Mark Oskin,
Justin Hensley,
Diana Keen,
Frederic T. Chong,
Matthew K. Farrens,
Aneet Chopra:
Exploiting ILP in Page-based Intelligent Memory.
MICRO 1999: 208-218 |
| 1998 |
|---|
| 18 | EE | Jude A. Rivers,
Edward S. Tam,
Gary S. Tyson,
Edward S. Davidson,
Matthew K. Farrens:
Utilizing Reuse Information in Data Cache Management.
International Conference on Supercomputing 1998: 449-456 |
| 1996 |
|---|
| 17 | | Matthew K. Farrens:
Distributed Decentralized Computing.
ACM Comput. Surv. 28(4es): 28 (1996) |
| 1995 |
|---|
| 16 | EE | Gary S. Tyson,
Matthew K. Farrens,
John Matthews,
Andrew R. Pleszkun:
A modified approach to data cache management.
MICRO 1995: 93-103 |
| 1994 |
|---|
| 15 | | Matthew K. Farrens,
Gary S. Tyson,
Andrew R. Pleszkun:
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.
ISCA 1994: 338-347 |
| 1993 |
|---|
| 14 | EE | Matthew K. Farrens,
Pius Ng,
Phil Nico:
A comparision of superscalar and decoupled access/execute architectures.
MICRO 1993: 100-103 |
| 13 | EE | Gary S. Tyson,
Matthew K. Farrens:
Techniques for extracting instruction level parallelism on MIMD architectures.
MICRO 1993: 128-137 |
| 1992 |
|---|
| 12 | | Matthew K. Farrens,
Arvin Park,
Allison Woodruff:
CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension.
IPPS 1992: 573-577 |
| 11 | EE | Gary S. Tyson,
Matthew K. Farrens,
Andrew R. Pleszkun:
MISC: a Multiple Instruction Stream Computer.
MICRO 1992: 193-196 |
| 10 | EE | Matthew K. Farrens,
Arvin Park,
Gary S. Tyson:
Modifying VM hardware to reduce address pin requirements.
MICRO 1992: 210-213 |
| 1991 |
|---|
| 9 | EE | Matthew K. Farrens,
Arvin Park:
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width.
ISCA 1991: 128-137 |
| 8 | EE | Matthew K. Farrens,
Andrew R. Pleszkun:
Strategies for Achieving Improved Processor Throughput.
ISCA 1991: 362-369 |
| 7 | EE | Jeffrey C. Becker,
Arvin Park,
Matthew K. Farrens:
An Analysis of the Information Content of Address Reference Streams.
MICRO 1991: 19-24 |
| 6 | EE | Matthew K. Farrens,
Arvin Park:
Workload and Implementation Considerations for Dynamic Base Register Caching.
MICRO 1991: 62-68 |
| 5 | EE | Matthew K. Farrens,
Brad Wetmore,
Allison Woodruff:
Alleviation of tree saturation in multistage interconnection networks.
SC 1991: 400-409 |
| 4 | | Matthew K. Farrens,
Andrew R. Pleszkun:
Implementation of the PIPE Processor.
IEEE Computer 24(1): 65-69 (1991) |
| 1990 |
|---|
| 3 | EE | Arvin Park,
Matthew K. Farrens:
Address compression through base register caching.
MICRO 1990: 193-199 |
| 2 | EE | Matthew K. Farrens,
Andrew R. Pleszkun:
An evaluation of functional unit lengths for single-chip processors.
MICRO 1990: 209-215 |
| 1989 |
|---|
| 1 | EE | Matthew K. Farrens,
Andrew R. Pleszkun:
Improving Performance of Small On-Chip Instruction Caches.
ISCA 1989: 234-241 |
