William J. Schilp

2000
3	EE	Peter M. Maurer, William J. Schilp: State-Machine Based Logic Simulation Using Three Logic Values. VLSI Design 2000: 430-435
1999
2	EE	Peter M. Maurer, William J. Schilp: Software Bit-Slicing: A Technique for Improving Simulation Performance. DATE 1999: 786-787
1996
1	EE	William J. Schilp, Peter M. Maurer: Unit delay simulation with the inversion algorithm. ICCAD 1996: 412-417

Coauthor Index

1

Peter M. Maurer

[1] [2] [3]