| |
| 2006 | ||
|---|---|---|
| 4 | EE | Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang: Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS 2006 |
| 2005 | ||
| 3 | EE | Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang: A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) 2005: 1174-1177 |
| 2004 | ||
| 2 | Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang: Static divided word matching line for low-power Content Addressable Memory design. ISCAS (2) 2004: 629-632 | |
| 2003 | ||
| 1 | EE | Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen: BIST for clock jitter measurements. ISCAS (5) 2003: 577-580 |
| 1 | Shu-Ming Chang | [3] |
| 2 | Zong-Shen Chen | [1] |
| 3 | Kuo-Hsing Cheng | [1] [2] [3] [4] |
| 4 | Chan-Wei Huang | [4] |
| 5 | Chia-Hung Wei | [2] |
| 6 | Wei-Bin Yang | [3] |