| |
| 2007 | ||
|---|---|---|
| 4 | EE | Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. GLOBECOM 2007: 265-270 |
| 3 | EE | Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: Serial Sum-Product Architecture for Low-Density Parity-Check Codes. ICCCN 2007: 154-158 |
| 2006 | ||
| 2 | EE | Hao Zhong, Tong Zhang, Erich F. Haratsch: High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor. ISCAS 2006 |
| 2000 | ||
| 1 | Erich F. Haratsch, Andrew J. Blanksby, Kamran Azadet: Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback. ICC (1) 2000: 372-376 | |
| 1 | Kamran Azadet | [1] |
| 2 | Andrew J. Blanksby | [1] |
| 3 | Ruwan N. S. Ratnayake | [3] [4] |
| 4 | Gu-Yeon Wei | [3] [4] |
| 5 | Tong Zhang | [2] |
| 6 | Hao Zhong | [2] |