Yong-Cheol Bae
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2004
1
Yong-Cheol Bae,
Gu-Yeon Wei
: A mixed PLL/DLL architecture for low jitter clock generation.
ISCAS (4) 2004
: 788-791
Coauthor
Index
1
Gu-Yeon Wei
[
1
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Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
