| |
| 2007 | ||
|---|---|---|
| 3 | EE | Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. GLOBECOM 2007: 265-270 |
| 2 | EE | Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: Serial Sum-Product Architecture for Low-Density Parity-Check Codes. ICCCN 2007: 154-158 |
| 2004 | ||
| 1 | Ruwan N. S. Ratnayake, Gu-Yeon Wei, Aleksandar Kavcic: Pipelined parallel architecture for high throughput MAP detectors. ISCAS (2) 2004: 505-508 | |
| 1 | Erich F. Haratsch | [2] [3] |
| 2 | Aleksandar Kavcic | [1] |
| 3 | Gu-Yeon Wei | [1] [2] [3] |