| |
| 2008 | ||
|---|---|---|
| 2 | EE | Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz: Processor Performance Modeling using Symbolic Simulation. ISPASS 2008: 127-138 |
| 2007 | ||
| 1 | EE | Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman: Robust Energy-Efficient Adder Topologies. IEEE Symposium on Computer Arithmetic 2007: 16-28 |
| 1 | Rajesh Ananthraman | [1] |
| 2 | Jamison D. Collins | [2] |
| 3 | Ron Ho | [1] |
| 4 | Mark Horowitz | [1] [2] |
| 5 | Dinesh Patil | [1] [2] |
| 6 | Hong Wang | [2] |