| |
| 2008 | ||
|---|---|---|
| 2 | EE | Chua-Chin Wang, Gang-Neng Sung, Chi-Chun Huang, Ching-Li Lee, Tian-Hau Chen, Wun-Ji Lin, Ron Hu: A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors. Journal of Circuits, Systems, and Computers 17(5): 943-956 (2008) |
| 2006 | ||
| 1 | EE | Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin: A 4-Kb low power 4-T SRAM design with negative word-line gate drive. ISCAS 2006 |
| 1 | Tian-Hau Chen | [2] |
| 2 | Ron Hu | [2] |
| 3 | Chi-Chun Huang | [2] |
| 4 | Ching-Li Lee | [1] [2] |
| 5 | Gang-Neng Sung | [2] |
| 6 | Chua-Chin Wang | [1] [2] |