The Journal of VLSI Signal Processing, Volume 5

Volume 5, Number 1, January 1993

• Tomás Lang, Jaime H. Moreno:
  Introduction. 6
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• Jens Franzen:
  A design method for on-line reconfigurable array processors. 21-35
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• V. Hecht, Karsten Rönner, Peter Pirsch:
  A defect-tolerant systolic array implementation for real time image processing. 37-47
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• J. L. Hueso, Gloria Martínez, Gloria Hernández:
  A systolic algorithm for the triangular Stein equation. 49-55
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• Mohammed Ahmed Ghouse:
  2D grid architectures for the DFT and the 2D DFT. 57-74
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• Ross Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken:
  A programmable floating-point cell for systolic signal processing. 75-83
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• Robert Cypher, C. Bernard Shung:
  Generalized trace-back techniques for survivor memory management in the Viterbi algorithm. 85-94
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• J. Canaris:
  A VLSI architecture for the real time computation of discrete trigonometric transforms. 95-104
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Volume 5, Numbers 2-3, April 1993

• Takao Nishitani, Peng H. Ang, Francky Catthoor:
  Introduction. 113
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• Tatsuo Ishiguro:
  VLSI in picture coding. 115-120
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• Robert Forchheimer, Keping Chen, Christer Svensson, Anders Ödmark:
  Single-chip image sensors with a digital processor array. 121-131
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• Hiroyuki Nakahira, Masakatsu Maruyama, Hideshi Ueda, Haruyasu Yamada:
  An image processing system using Image Signal Multiprocessors (ISMPs). 133-140
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• Peter A. Ruetz, Po Tong, Daniel Luthi, Peng H. Ang:
  A video-rate JPEG chip set. 141-150
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• Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi:
  DCT/IDCT processor for HDTV developed with dsp silicon compiler. 151-158
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• Klaus Gaedke, Hartwig Jeschke, Peter Pirsch:
  A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications. 159-169
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• Marc Engels, Rudy Lauwereins, J. A. Peperstraete, Arthur H. M. van Roermund:
  Design of a processing board for a programmable multi-VSP system. 171-184
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• Ji-chien Lee, Bing J. Sheu, Rama Chellappa:
  A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture. 185-199
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• Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten:
  Architectural strategies for high-throughput applications. 201-220
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• Toon Gijbels, Francky Catthoor, Luc Van Eycken, André Oosterlinck, Hugo De Man:
  An application-specific architecture for the RBN-coder with efficient memory organization. 221-235
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• C. V. Reventlow, M. Talmi, S. Wolf, M. Ernst, K. Müller, C. Stoffers:
  System considerations and the system level design of a chip set for real-time TV and HDTV motion estimation. 237-248
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• Ravi K. Kolagotla, Shu-sun Yu, Joseph Jájá:
  Systolic architectures for finite-state vector quantization. 249-259
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• Robert L. Stevenson, George B. Adams, Leah H. Jamieson, Edward J. Delp:
  Parallel implementation for iterative image restoration algorithms on a parallel DSP machine. 261-272
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• Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai:
  An optimization technique for lowering the iteration bound of DSP programs. 273-282
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