Fredrik Dahlgren

2007
34	EE	Fredrik Dahlgren: Partial Continuous Functions and Admissible Domain Representations. J. Log. Comput. 17(6): 1063-1081 (2007)
2006
33	EE	Fredrik Dahlgren: Partial Continuous Functions and Admissible Domain Representations. CiE 2006: 94-104
2004
32	EE	Fredrik Dahlgren: Computability and continuity in metric partial algebras equipped with computability structures. Math. Log. Q. 50(4-5): 486-500 (2004)
2002
31	EE	Magnus Ekman, Per Stenström, Fredrik Dahlgren: TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ISLPED 2002: 243-246
2001
30	EE	Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec: Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par 2001: 385
29	EE	Fredrik Dahlgren: Future Mobile Phones--Complex Design Challenges from an Embedded Systems Perspective. ICECCS 2001: 92-
2000
28	EE	Magnus Karlsson, Fredrik Dahlgren, Per Stenström: A Prefetching Technique for Irregular Accesses to Linked Data Structures. HPCA 2000: 206-217
27	EE	Martin Kämpe, Fredrik Dahlgren: Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. IPDPS 2000: 163-170
26	EE	Jim Nilsson, Fredrik Dahlgren: Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors. IPDPS 2000: 684-692
25	EE	Ashley Saulsbury, Fredrik Dahlgren, Per Stenström: Recency-based TLB preloading. ISCA 2000: 117-127
1999
24	EE	Jim Nilsson, Fredrik Dahlgren: Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. ICPP 1999: 246-
23	EE	Ashley Saulsbury, Su-Jaen Huang, Fredrik Dahlgren: Efficient management of memory hierarchies in embedded DRAM systems. International Conference on Supercomputing 1999: 464-473
22		Fredrik Dahlgren, Josep Torrellas: Cache-Only Memory Architectures. IEEE Computer 32(6): 72-79 (1999)
21		Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström: Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. J. Parallel Distrib. Comput. 56(2): 122-143 (1999)
20		Fredrik Dahlgren: Techniques for Improving Performance of Hybrid Snooping Cache Protocols. J. Parallel Distrib. Comput. 59(3): 329-359 (1999)
1998
19	EE	Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal: The Sensitivity of Communication Mechanisms to Bandwidth and Latency. HPCA 1998: 37-46
18		Fredrik Dahlgren, Michel Dubois, Per Stenström: Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. IEEE Trans. Computers 47(10): 1041-1055 (1998)
1997
17	EE	Fredrik Dahlgren, Anders Landin: Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors. HPCA 1997: 14-23
16		Fredrik Dahlgren, Per Stenström, Mårten Björkman: Reducing the Read-Miss Penalty for Flat COMA Protocols. Comput. J. 40(4): 208-219 (1997)
15		Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois: Boosting the Performance of Shared Memory Multiprocessors. IEEE Computer 30(7): 63-70 (1997)
1996
14	EE	Anders Landin, Fredrik Dahlgren: Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. HPCA 1996: 95-105
13		Per Stenström, Fredrik Dahlgren: Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). IEEE Computer 29(12): 29-31 (1996)
12	EE	Fredrik Dahlgren, Per Stenström: Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 7(4): 385-398 (1996)
1995
11	EE	Mårten Björkman, Fredrik Dahlgren, Per Stenström: Using hints to reduce the read miss penalty for flat COMA protocols. HICSS (1) 1995: 242-251
10		Fredrik Dahlgren, Per Stenström: Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. HPCA 1995: 68-77
9	EE	Fredrik Dahlgren: Boosting the Performance of Hybrid Snooping Cache Protocols. ISCA 1995: 60-69
8	EE	Fredrik Dahlgren, Michel Dubois, Per Stenström: Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 6(7): 733-746 (1995)
7		Fredrik Dahlgren, Per Stenström: Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. J. Parallel Distrib. Comput. 26(2): 193-210 (1995)
1994
6		Fredrik Dahlgren, Per Stenström: Reducing the Write Traffic for a Hybrid Cache Protocol. ICPP (1) 1994: 166-173
5		Fredrik Dahlgren, Michel Dubois, Per Stenström: Combined Performance Gains of Simple Cache Protocol Extensions. ISCA 1994: 187-197
1993
4		Fredrik Dahlgren, Michel Dubois, Per Stenström: Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. ICPP 1993: 56-63
1991
3	EE	Fredrik Dahlgren: A program-driven simulation model of an MIMD multiprocessor. Annual Simulation Symposium 1991: 40-49
2		Per Stenström, Fredrik Dahlgren, Lars Lundberg: A Lockup-Free Multiprocessor Cache Design. ICPP (1) 1991: 246-250
1	EE	Fredrik Dahlgren, Per Stenström: On Reconfigurable On-Chip Data Caches. MICRO 1991: 189-198

Coauthor Index

1	Anant Agarwal	[19]
2	Eduard Ayguadé	[30]
3	Rajeev Barua	[19]
4	Mårten Björkman	[11] [16]
5	Mats Brorsson	[15]
6	Frederic T. Chong	[19]
7	Michel Dubois	[4] [5] [8] [15] [18]
8	Christine Eisenbeis	[30]
9	Magnus Ekman	[31]
10	Roger Espasa	[30]
11	Guang R. Gao	[30]
12	Håkan Grahn	[15]
13	Su-Jaen Huang	[23]
14	Martin Kämpe	[27]
15	Magnus Karlsson	[28]
16	John Kubiatowicz	[19]
17	Anders Landin	[14] [17]
18	Lars Lundberg	[2]
19	Henk L. Muller	[30]
20	Jim Nilsson	[24] [26]
21	Rizos Sakellariou	[30]
22	Ashley Saulsbury	[23] [25]
23	André Seznec	[30]
24	Jonas Skeppstedt	[21]
25	Per Stenström	[1] [2] [4] [5] [6] [7] [8] [10] [11] [12] [13] [15] [16] [18] [21] [25] [28] [31]
26	Josep Torrellas	[22]

Colors in the list of coauthors