| |
| 2008 | ||
|---|---|---|
| 3 | EE | Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner: Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. NOCS 2008: 139-148 |
| 2007 | ||
| 2 | EE | Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner: Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. DATE 2007: 1090-1095 |
| 1 | EE | Ivan Miro Panades, Alain Greiner: Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. NOCS 2007: 83-94 |
| 1 | Fabien Clermidy | [3] |
| 2 | Alain Greiner | [1] [2] [3] |
| 3 | Abbas Sheibanyrad | [2] |
| 4 | Pascal Vivet | [3] |