| 2003 |
|---|
| 8 | EE | Nikos Pitsianis,
Gerald G. Pechanek:
Indirect VLIW memory allocation for the ManArray multiprocessor DSP.
SIGARCH Computer Architecture News 31(1): 69-74 (2003) |
| 2000 |
|---|
| 7 | EE | Gerald G. Pechanek,
Stamatis Vassiliadis:
The ManArray( Embedded Processor Architecture.
EUROMICRO 2000: 1348-1355 |
| 6 | EE | Bruce Schulman,
Gerald G. Pechanek:
A 90k Gate ``CLB'' for Parallel Distributed Computing.
IPDPS Workshops 2000: 831-838 |
| 1999 |
|---|
| 5 | EE | Gerald G. Pechanek,
Stamatis Vassiliadis,
Nikos Pitsianis:
ManArray Processor Interconnection Network: An Introduction.
Euro-Par 1999: 761-765 |
| 1998 |
|---|
| 4 | EE | Stamatis Vassiliadis,
Edwin A. Hakkennes,
J. S. S. M. Wong,
Gerald G. Pechanek:
The Sum-Absolute-Difference Motion Estimation Accelerato.
EUROMICRO 1998: 20559-20566 |
| 1996 |
|---|
| 3 | EE | Chris H. L. Moller,
Gerald G. Pechanek:
Architectural simulation system for M.f.a.s.t.
Annual Simulation Symposium 1996: 221- |
| 1995 |
|---|
| 2 | EE | Gerald G. Pechanek,
M. Stojancic,
Stamatis Vassiliadis,
C. John Glossner:
MFAST: a single chip highly parallel image processing architecture.
ICIP 1995: 69-72 |
| 1 | | Valentine C. Aikens II,
Steven M. Barber,
José G. Delgado-Frias,
Gerald G. Pechanek,
Stamatis Vassiliadis:
A Neuro-Architecture with Embedded Learning.
Parallel and Distributed Computing and Systems 1995: 103-106 |
