| |
| 2006 | ||
|---|---|---|
| 4 | EE | Suryanarayana Tatapudi, José G. Delgado-Frias: A mesochronous pipeline scheme for high performance low power digital systems. ISCAS 2006 |
| 2005 | ||
| 3 | Suryanarayana Tatapudi, José G. Delgado-Frias: A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES 2005: 191-197 | |
| 2 | EE | Suryanarayana Tatapudi, José G. Delgado-Frias: A High Performance Hybrid Wave-Pipelined Multiplier. ISVLSI 2005: 282-283 |
| 2003 | ||
| 1 | EE | Suryanarayana Tatapudi, Valeriu Beiu: Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL). IWANN (2) 2003: 49-56 |
| 1 | Valeriu Beiu | [1] |
| 2 | José G. Delgado-Frias | [2] [3] [4] |