| 2008 |
|---|
| 20 | EE | Po-Chun Chang,
I-Wei Wu,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor.
DAC 2008: 776-779 |
| 19 | EE | I-Wei Wu,
Zhi-Yuan Chen,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Instruction Set Extension Exploration in Multiple-Issue Architecture.
DATE 2008: 764-769 |
| 2007 |
|---|
| 18 | EE | I-Wei Wu,
Shih-Chia Huang,
Chung-Ping Chung,
Jean Jyh-Jiun Shann:
Instruction Set Extension Generation with Considering Physical Constraints.
HiPEAC 2007: 291-305 |
| 2006 |
|---|
| 17 | EE | Kuen-Cheng Chiang,
Zhi-Wei Chen,
Jean Jyh-Jiun Shann:
Design and implementation of a reconfigurable hardware for secure embedded systems.
ASIACCS 2006: 364 |
| 16 | EE | Cher-Sheng Cheng,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems.
Inf. Process. Manage. 42(2): 407-428 (2006) |
| 15 | EE | Cher-Sheng Cheng,
Chung-Ping Chung,
Jean Jyh-Jiun Shann:
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems.
Inf. Process. Manage. 42(3): 729-750 (2006) |
| 2005 |
|---|
| 14 | | Wei-Hao Chiao,
Tsung-Hsi Weng,
Jean Jyh-Jiun Shann,
Chung-Ping Chung,
Jimmy Lu:
Low-Power Data Address Bus Encoding Method.
CDES 2005: 204-210 |
| 13 | | Yau-Chong Hu,
Wei-Hau Chiao,
Jean Jyh-Jiun Shann,
Chung-Ping Chung,
Wen-Feng Chen:
Low-Power Branch Prediction.
CDES 2005: 211-217 |
| 2004 |
|---|
| 12 | EE | Cher-Sheng Cheng,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems.
ITCC (2) 2004: 229-235 |
| 11 | EE | Kelvin Lin,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Code compression by register operand dependency.
Journal of Systems and Software 72(3): 295-304 (2004) |
| 10 | EE | Lee-Ren Ton,
Lung-Chung Chang,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
A software/hardware cooperated stack operations folding model for Java processors.
Journal of Systems and Software 72(3): 377-387 (2004) |
| 2003 |
|---|
| 9 | EE | Kelvin Lin,
Chung-Ping Chung,
Jean Jyh-Jiun Shann:
Compressing MIPS code by multiple operand dependencies.
ACM Trans. Embedded Comput. Syst. 2(4): 482-508 (2003) |
| 8 | EE | Wann-Yun Shieh,
Tien-Fu Chen,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Inverted file compression through document identifier reassignment.
Inf. Process. Manage. 39(1): 117-131 (2003) |
| 7 | EE | Wann-Yun Shieh,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
An Inverted File Cache for Fast Information Retrieval.
J. Inf. Sci. Eng. 19(4): 681-695 (2003) |
| 2002 |
|---|
| 6 | EE | Kelvin Lin,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Code Compression by Register Operand Dependency.
Interaction between Compilers and Computer Architectures 2002: 91-101 |
| 5 | EE | Lee-Ren Ton,
Lung-Chung Chang,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Design of an optimal folding mechanism for Java processors.
Microprocessors and Microsystems 26(8): 341-352 (2002) |
| 2001 |
|---|
| 4 | EE | R.-Ming Shiu,
Hui-Yue Hwang,
Jean Jyh-Jiun Shann:
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors.
J. Inf. Sci. Eng. 17(5): 787-803 (2001) |
| 1998 |
|---|
| 3 | EE | S.-K. Cheng,
R.-Ming Shiu,
Jean Jyh-Jiun Shann:
Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors.
ICPADS 1998: 488-495 |
| 2 | EE | Hui-Yue Hwang,
R.-Ming Shiu,
Jean Jyh-Jiun Shann:
An X86 Load/Store Unit with Aggressive Scheduling of Load/Store Operations.
ICPADS 1998: 496-503 |
| 1994 |
|---|
| 1 | EE | Hsin-Chia Fu,
Jean Jyh-Jiun Shann:
A Fuzzy Neural Network for Knowledge Learning.
Int. J. Neural Syst. 5(1): 13-22 (1994) |
