Y. Tsiatouhas
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
---|---|---|
25 | EE | Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni: A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers 57(8): 1032-1045 (2008) |
2007 | ||
24 | EE | Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou: Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. VLSI Syst. 15(4): 461-465 (2007) |
2006 | ||
23 | EE | Y. Tsiatouhas, Angela Arapoyanni: High fan-in differential current mirror logic. ISCAS 2006 |
2005 | ||
22 | EE | Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou: Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS 2005: 149-156 |
21 | EE | Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni: A Built-In Self-Test Scheme for Differential Ring Oscillators. ISQED 2005: 448-452 |
20 | EE | A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil: The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. ISVLSI 2005: 270-271 |
2004 | ||
19 | EE | A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky: A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. IOLTS 2004: 52-57 |
18 | EE | Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni: Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . ISVLSI 2004: 293-296 |
17 | EE | Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni: A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. J. Electronic Testing 20(2): 133-142 (2004) |
16 | EE | Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis: A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electronic Testing 20(5): 523-531 (2004) |
2003 | ||
15 | EE | Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis: A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. IOLTS 2003: 12-16 |
14 | EE | Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni: An Embedded IDDQ Testing Architecture and Technique. ISQED 2003: 442- |
2002 | ||
13 | EE | Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis: A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW 2002: 56-60 |
12 | EE | A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis: SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology. ISCAS (5) 2002: 145-148 |
11 | EE | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni: Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED 2002: 100-105 |
10 | EE | Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni: A new technique for IDDQ testing in nanometer technologies. Integration 31(2): 183-194 (2002) |
2001 | ||
9 | EE | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou: Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW 2001: 106-110 |
2000 | ||
8 | EE | Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos: A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE 2000: 756 |
7 | EE | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos: A Compact Built-In Current Sensor for IDDQ Testing. IOLTW 2000: 95-99 |
6 | EE | Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou: On Testability of Multiple Precharged Domino Logic. ISQED 2000: 299-304 |
5 | EE | G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni: Management of charge pump circuits. Integration 30(1): 91-101 (2000) |
1999 | ||
4 | EE | Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas: Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE 1999: 112-116 |
3 | EE | Y. Tsiatouhas, Th. Haniotakis: A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. DFT 1999: 95-100 |
2 | EE | Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis: On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI 1999: 20-23 |
1998 | ||
1 | EE | Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas: C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. DFT 1998: 155-163 |
1 | Angela Arapoyanni (Aggeliki Arapoyanni) | [5] [8] [10] [11] [12] [13] [14] [15] [16] [17] [18] [21] [22] [23] [25] |
2 | A. Chrisanthopoulos | [5] [12] |
3 | Lampros Dermentzoglou | [17] [21] |
4 | H. Djemil | [20] |
5 | Costas Efstathiou | [6] [9] [24] |
6 | Aristides Efthymiou | [22] |
7 | Themistoklis Haniotakis (Th. Haniotakis) | [1] [2] [3] [4] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18] [19] [20] [22] [24] [25] |
8 | V. Kaky | [19] |
9 | G. Kamoulakos | [5] |
10 | Sotirios Matakias | [15] [16] [18] [22] [25] |
11 | Yiannis Moisiadis | [10] |
12 | Michael Nicolaidis | [2] |
13 | Dimitris Nikolos | [1] [2] [4] [6] [7] [8] [9] [10] [11] [13] [24] |
14 | A. Rao | [19] [20] |
15 | Haridimos T. Vergos | [2] [4] |