Jing-Shiun Lin

2006
2	EE	Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin, Wen-Tsai Sheu: Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). APCCAS 2006: 2020-2023
1	EE	Jing-Shiun Lin, Chung-Kung Lee, Ming-Der Shieh, Jun-Hong Chen: High-speed CRC design for 10 Gbps applications. ISCAS 2006

Coauthor Index

1	Jun-Hong Chen	[1]
2	Chung-Kung Lee	[1]
3	Su-Hon Lin	[2]
4	Ming-Hwa Sheu	[2]
5	Wen-Tsai Sheu	[2]
6	Ming-Der Shieh	[1]