Chao-Hsiang Wang

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2008

1 EE Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang: Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2ⁿ, 2ⁿ⁺¹ - 1, 2ⁿ - 1). IEICE Transactions 91-D(7): 2058-2060 (2008)

2008
1	EE	Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang: Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2ⁿ, 2ⁿ⁺¹ - 1, 2ⁿ - 1). IEICE Transactions 91-D(7): 2058-2060 (2008)

Coauthor Index

1 Su-Hon Lin [1]

2 Ming-Hwa Sheu [1]