Richard E. Matick

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8EERichard E. Matick, Stanley Schuster: Logic-based eDRAM: Origins and rationale for use. IBM Journal of Research and Development 49(1): 145-166 (2005)
7EERichard E. Matick: Comparison of analytic performance models using closed mean-value analysis versus open-queuing theory for estimating cycles per instruction of memory hierarchies. IBM Journal of Research and Development 47(4): 495-517 (2003)
6EERichard E. Matick, Thomas J. Heller, Michael Ignatowski: Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory. IBM Journal of Research and Development 45(6): 819-842 (2001)
5EERichard E. Matick: Modular nets (MNETS): A modular design methodology for computer timers. IBM Journal of Research and Development 42(6): 813-830 (1998)
4 Richard E. Matick, Robert Mao, Samuel Ray: Architecture, Design, and Operating Characteristics of a 12-ns CMOS Functional Cache Chip. IBM Journal of Research and Development 33(5): 524-539 (1989)
3 Richard E. Matick: Impact of Memory Systems on Computer Architecture and System Organization. IBM Systems Journal 25(3/4): 274-305 (1986)
2 Richard E. Matick, Daniel T. Ling, Satish Gupta, Frederick Dill: All Points Addressable Raster Display Memory. IBM Journal of Research and Development 28(4): 379-392 (1984)
1 Richard E. Matick, Daniel T. Ling: Architecture Implications in the Design of Microprocessors. IBM Systems Journal 23(3): 264-280 (1984)

Coauthor Index

1Frederick Dill [2]
2Satish Gupta [2]
3Thomas J. Heller [6]
4Michael Ignatowski [6]
5Daniel T. Ling [1] [2]
6Robert Mao [4]
7Samuel Ray [4]
8Stanley Schuster [8]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)