| 2005 |
|---|
| 8 | EE | Richard E. Matick,
Stanley Schuster:
Logic-based eDRAM: Origins and rationale for use.
IBM Journal of Research and Development 49(1): 145-166 (2005) |
| 2003 |
|---|
| 7 | EE | Richard E. Matick:
Comparison of analytic performance models using closed mean-value analysis versus open-queuing theory for estimating cycles per instruction of memory hierarchies.
IBM Journal of Research and Development 47(4): 495-517 (2003) |
| 2001 |
|---|
| 6 | EE | Richard E. Matick,
Thomas J. Heller,
Michael Ignatowski:
Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory.
IBM Journal of Research and Development 45(6): 819-842 (2001) |
| 1998 |
|---|
| 5 | EE | Richard E. Matick:
Modular nets (MNETS): A modular design methodology for computer timers.
IBM Journal of Research and Development 42(6): 813-830 (1998) |
| 1989 |
|---|
| 4 | | Richard E. Matick,
Robert Mao,
Samuel Ray:
Architecture, Design, and Operating Characteristics of a 12-ns CMOS Functional Cache Chip.
IBM Journal of Research and Development 33(5): 524-539 (1989) |
| 1986 |
|---|
| 3 | | Richard E. Matick:
Impact of Memory Systems on Computer Architecture and System Organization.
IBM Systems Journal 25(3/4): 274-305 (1986) |
| 1984 |
|---|
| 2 | | Richard E. Matick,
Daniel T. Ling,
Satish Gupta,
Frederick Dill:
All Points Addressable Raster Display Memory.
IBM Journal of Research and Development 28(4): 379-392 (1984) |
| 1 | | Richard E. Matick,
Daniel T. Ling:
Architecture Implications in the Design of Microprocessors.
IBM Systems Journal 23(3): 264-280 (1984) |
