| 2007 |
|---|
| 3 | EE | Yoshihide Komatsu,
Koichiro Ishibashi,
Makoto Nagata:
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias.
IEICE Transactions 90-C(4): 692-698 (2007) |
| 2006 |
|---|
| 2 | EE | Koichiro Ishibashi,
Tetsuya Fujimoto,
Takahiro Yamashita,
Hiroyuki Okada,
Yukio Arima,
Yasuyuki Hashimoto,
Kohji Sakata,
Isao Minematsu,
Yasuo Itoh,
Haruki Toda,
Motoi Ichihashi,
Yoshihide Komatsu,
Masato Hagiwara,
Toshiro Tsukada:
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.
IEICE Transactions 89-C(3): 250-262 (2006) |
| 1 | EE | Yoshihide Komatsu,
Yukio Arima,
Koichiro Ishibashi:
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond.
IEICE Transactions 89-C(3): 384-391 (2006) |
