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| 2006 | ||
|---|---|---|
| 1 | EE | Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa: An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Transactions 89-C(11): 1535-1543 (2006) |
| 1 | Mitsuya Fukazawa | [1] |
| 2 | Masaaki Hirata | [1] |
| 3 | Makoto Nagata | [1] |
| 4 | Kazuhiro Satoh | [1] |
| 5 | Kenji Shimazaki | [1] |
| 6 | Hiroyuki Tsujikawa | [1] |