| 2008 |
|---|
| 10 | EE | Qiong Cai,
Josep M. Codina,
José González,
Antonio González:
A software-hardware hybrid steering mechanism for clustered microarchitectures.
IPDPS 2008: 1-12 |
| 2007 |
|---|
| 9 | EE | Alex Aletà,
Josep M. Codina,
Antonio González,
David R. Kaeli:
Heterogeneous Clustered VLIW Microarchitectures.
CGO 2007: 354-366 |
| 8 | EE | Josep M. Codina,
F. Jesús Sánchez,
Antonio González:
Virtual Cluster Scheduling Through the Scheduling Graph.
CGO 2007: 89-101 |
| 2005 |
|---|
| 7 | EE | Alex Aletà,
Josep M. Codina,
Antonio González,
David R. Kaeli:
Demystifying on-the-fly spill code.
PLDI 2005: 180-189 |
| 2004 |
|---|
| 6 | EE | Alex Aletà,
Josep M. Codina,
Antonio González,
David R. Kaeli:
Removing communications in clustered microarchitectures through instruction replication.
TACO 1(2): 127-151 (2004) |
| 2003 |
|---|
| 5 | EE | Alex Aletà,
Josep M. Codina,
Antonio González,
David R. Kaeli:
Instruction Replication for Clustered Microarchitectures.
MICRO 2003: 326-338 |
| 2002 |
|---|
| 4 | EE | Josep M. Codina,
Josep Llosa,
Antonio González:
A comparative study of modulo scheduling techniques.
ICS 2002: 97-106 |
| 3 | EE | Alex Aletà,
Josep M. Codina,
F. Jesús Sánchez,
Antonio González,
David R. Kaeli:
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning.
IEEE PACT 2002: 281-290 |
| 2001 |
|---|
| 2 | EE | Josep M. Codina,
F. Jesús Sánchez,
Antonio González:
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors.
IEEE PACT 2001: 175-184 |
| 1 | EE | Alex Aletà,
Josep M. Codina,
F. Jesús Sánchez,
Antonio González:
Graph-partitioning based instruction scheduling for clustered processors.
MICRO 2001: 150-159 |
