2001 | ||
---|---|---|
2 | EE | Victor V. Zyuban, D. Meltzer: Clocking strategies and scannable latches for low power appliacations. ISLPED 2001: 346-351 |
2000 | ||
1 | EE | Stephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia: "Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717 |
1 | N. Aoki | [1] |
2 | David Boerstler | [1] |
3 | P. Coulman | [1] |
4 | Sang H. Dhong | [1] |
5 | Brian K. Flachs | [1] |
6 | H. Peter Hofstee | [1] |
7 | N. Kojima | [1] |
8 | Ohsang Kwon | [1] |
9 | K. Lee | [1] |
10 | Kevin J. Nowka | [1] |
11 | J. Park | [1] |
12 | J. Peter | [1] |
13 | Stephen D. Posluszny | [1] |
14 | Joel Silberman | [1] |
15 | Osamu Takahashi | [1] |
16 | Paul G. Villarrubia (Paul Villarrubia) | [1] |
17 | Victor V. Zyuban | [2] |